TIA 1A - TELEVISION INTERFACE ADAPTOR (MODEL 1A)
11. Audio Circuits
Two audio circuits are incorporated on this chip. They are
identical and completely independent, although their
outputs could be combined externally into one speaker.
Each audio circuit consists of parts described below, and
in figure 7.
A. Frequency Select
Clock pulses (at approximately 30 KHz) from the horizontal
sync counter pass through a divide by N circuit which is
controlled by the output code from a five bit frequency
register (AUDF). This register can be loaded (written) by
the microprocessor at any time, and causes the 30 KHz
clocks to be divided by 1 (code 00000) through 32 (code
11111). This produces pulses that are digitally adjustable
from approximately 30 KHz to 1 KHz and are used to clock
the noise-tone generator.
B. Noise-Tone Generator
This circuit contains a nine bit shift counter which may be
controlled by the output code from a four bit audio control
register(AUDC), and is clocked by the frequency select
circuit. The control register can be loaded by the
microprocessor at any time, and selects different shift
counter feedback taps and count lengths to produce a
variety of noise and tone qualities.
C. Volume Select
The shift counter output is used to drive the audio output
pad through four driver transistors that are graduated in
size. Each transistor is twice as large as the previous one
and is enable by one bit from the audio volume register
(AUDV). This audio volume register may be loaded by the
microprocessor at any time. As binary codes 0 through 15
are loaded, the pad drive transistors are enabled in a
binary sequence. The shift counter output therefore can
pull down on the audio output pad with 16 selectable
impedance levels.